The following will explain one example of a conventional image display device, i.e. an active matrix type liquid crystal display device. As shown in FIG. 9, this image display device is made up of a pixel array ARY, a scanning signal line driving circuit GD, a data signal line driving circuit SD and a pre-charging circuit PC.
The pixel array ARY includes a plurality of scanning signal lines GL and a plurality of data signal lines SL crossing one another, and pixel PIX which is arranged in a matrix is formed within each area enclosed by two adjacent scanning signal lines GL and two adjacent data signal lines SL. A display section displays an image by writing a video signal DAT from each data signal line SL into each pixel PIX in synchronism with a scanning signal outputted from each scanning signal line GL.
As shown in FIG. 10, the pixel PIX is made up of a switching element SW, a liquid crystal capacitor CL and an auxiliary capacitor Cs. A pixel capacitor Cp is a sum of the liquid crystal capacitor CL and auxiliary capacitor Cs. The data signal line driving circuit SD makes sampling of the video signal DAT which was inputted by an analog switch, in synchronism with a timing signal such as a clock signal CKS and a data start signal SPS, and writes the received video signal DAT into each data signal line SL as required.
The scanning signal line driving circuit GD successively selects the scanning signal line GL in synchronism with the timing signal such as the clock signal CKG, a scanning start signal SPG and a pulse width control signal PWC, and carries out opening and closing of the switching element SW within the pixel PIX, thereby writing the video signal DAT which was inputted to each data signal line SL into each pixel PIX, and holding the video signal DAT which was written into the capacitors within each pixel PIX.
The pre-charging circuit PC makes sampling of a pre-charging voltage PCV which was inputted in synchronism with a timing of a pre-charging control signal PCC, and writes the pre-charging voltage PCV before the video signal DAT is written into each data signal line SL.
By repeating the foregoing operations, an image can be displayed in the pixel array ARY.
FIG. 11 shows a timing chart of the foregoing operations. In FIG. 11, the video signal DAT is inputted in synchronism with the clock signal CKS and data start signal SPS of the data signal line driving circuit SD. A driving method of a horizontal line reversal system is adopted in this example, and a video signal having a positive polarity is written into a line which corresponds to a scanning signal line GLj (j≧1), while a video signal having a negative polarity is written into a line which corresponds to a scanning signal GLj+1. Further, in a horizontal retrace line period, the data signal line SL is charged to the pre-charging voltage PCV by the pre-charging control signal PCC. Here, polarities of the pre-charging voltage PCV and the video signal DAT to be written next are the same.
In recent years, as image display devices have been refined, a higher sampling rate has been adopted in the data signal line driving circuit SD. This, however, involves a problem of considerable deterioration of image quality caused by the video signal DAT which was incompletely written into the data signal line SL due to the higher sampling rate. Therefore, there has been adopted a method, which suppresses such deterioration of image quality by using the pre-charging circuit PC to pre-charge the pre-charging voltage PCV before writing the video signal DAT into the data signal line SL.
Referring to FIG. 9 which shows a conventional example of the image display device, the following will explain an operation thereof. The pre-charging circuit PC charges each data signal line SL with the pre-charging voltage PCV in synchronism with the timing of the pre-charging control signal PCC.
However, as shown in a timing chart of FIG. 11, in order to supply all of the data signal lines SL with the pre-charging voltage PCV in a short period of time, a group of switching elements which composes the pre-charging circuit PC is required to be large. Furthermore, since the group of the switching elements is collectively controlled, a large quantity of charges are transferred to each data signal line SL at once, thereby fluctuating the pre-charging voltage PCV.
When the fluctuating pre-charging voltage PCV does not return to its original state before the sampling thereof ends, a level of the pre-charging voltage PCV to be supplied to the data signal line SL becomes deficient. As a result, this may adversely affect a voltage of the video signal DAT to be written into the data signal line SL by the data signal line driving circuit SD, thus, deterioration of display may be resulted therefrom. Furthermore, an abrupt change in the pre-charging voltage PCV may trigger power fluctuation, which causes all of the control signals to become unstable, thereby possibly resulting in poor display.
As discussed, an attempt has been made to suppress fluctuation in the pre-charging voltage PCV, in which, as shown in FIG. 9, a current amplifying section is provided on a following stage of a control signal generating circuit CTL. However, this raises a new problem of increasing power consumption due to the current amplifying section thus provided.
Meanwhile, in recent years, an active-matrix liquid crystal display device has frequently been adopted to TV (television) monitors, portable information terminals and others. Therefore, video sources for display have been diversified, and it is often the case where an aspect ratio of a video or image to be displayed does not match an aspect ratio of a screen of a display device. For example, in one case, a liquid crystal display device which principally displays TV pictures according to an NTSC system is used to display a Hi-Vision broadcast of an MUSE system, etc., by converting it into the NTSC system. In the other case, a liquid crystal display device having an aspect ratio of 16:9 which principally displays TV images according to a Hi-Vision television standard is used to display TV pictures of the NTSC system having an aspect ratio of 4:3.
Generally, when displaying a picture or an image having an aspect ratio which does not match an aspect ratio of the screen of a display device (hereinafter referred to as “non-match image display mode”), and when, for example, displaying a video source having an aspect ratio of 16:9 by a liquid crystal display device having a screen aspect ratio of 4:3, a picture to be displayed by the liquid crystal display device may become such that, as shown in FIG. 24, black display occurs in upper and lower parts of the screen, or as shown in FIG. 25, the picture is cut on both sides. However, in the latter case where the height of the video source is adjusted to that of the screen when displaying, it is feasible that the reduced portion of the picture may contain important information. Therefore, commonly, the former in which the width of the video source is adjusted to that of the screen when displaying is more widely adopted. Note that, hereinafter, a “wide mode” refers to display of a video source having an aspect ratio of 16:9, and a “normal mode” refers to display of a video source having an aspect ratio of 4:3.
Further, a video camcorder, for example, often adopts a liquid crystal display device, where the most popular aspect ratio for a display screen is 4:3. However, nowadays, the screen of a TV which is larger in the width than the height (“wide TV”, hereinafter) has been the mainstream of home TVs, and when displaying a picture recorded by the video camcorder on this wide TV, upper and lower parts of the picture are lost. Therefore, in order to prevent such a partial loss of the picture have been taken measures; for example, a widely adopted method is such that, when videotaping by the video camcorder, as shown in FIG. 24, black display in the upper and lower parts is strategically carried out in advance during display of a picture by a liquid crystal display device of the video camcorder, thereby preventing the loss of the picture in the upper and lower parts on a screen of the wide TV.
On the other hand, as a system to display a picture having an aspect ratio of 4:3 by a display device which principally displays TV pictures according to the Hi-Vision television standard, proposed is a method such that a whole image is displayed in the center of a screen in the normal mode, where margins on both sides of the screen are given a mask of a black or arbitrarily selected color. For example, the Letters Patent of U.S. Pat. No. 5,625,376 (Date of Patent: Apr. 29, 1997) discloses an active matrix display device which has a pixel group, pixels of which are disposed along rows and columns on a wide screen, a gate line group, each gate line of which is connected to each row of pixels, a vertical driving circuit connected to the gate line group, a data line group each data line of which is connected to each column of pixels, signal lines, each of which supplies a picture signal from the outside, a sampling switch group which connects the signal lines and the data line group, and a horizontal shift register which controls successive opening and closing of the sampling switch group, wherein the columns of pixels on a wide screen are separated into a predetermined region for the normal display and an extended region for the wide mode display, the horizontal shift register is separated into extension stage portions, one of which corresponds to the columns of pixels in the predetermined region and the other the columns of pixels in the extended region, and in the normal mode, in the horizontal shift register, the predetermined stage portions and the extended stage portions are serially connected and integrated, while in the normal mode, the extended stage portions of the horizontal shift register are disconnected so as to successively carry out opening and closing of only a sampling switch pertaining to the predetermined region among the whole sampling switch group. Note that, in this display device, in the normal mode, data lines pertaining to the extended region on both ends of the screen are provided with signals of a fixed level by mask means so as to perform mask display in the extended region, while using the whole screen in the wide mode.
Among these liquid crystal display devices above, a conventional image display device which performs black display in the upper and lower parts of a screen includes an active matrix liquid crystal display device, that will be explained below. This image display device, as shown in FIG. 21, includes a pixel array ARY, a scanning signal line driving circuit GD, a data signal line driving circuit SD, a pre-charging circuit PC and a control signal generating circuit CTL. Further, as pre-charging voltage stabilizing means for stabilizing a pre-charging voltage PCV to be inputted to the pre-charging circuit, a current amplifying section Buffer is provided on a preceding stage of the pre-charging circuit PC.
The pixel array ARY has a plurality of scanning signal lines GLj (j=1 to n) and a plurality of data signal lines SDLi (i=1 to m) crossing each other, and the pixels PIX in matrix are each disposed in a portion enclosed by the two adjacent scanning signal lines GLj and the two adjacent data signal lines SDLi. A display section made up of the pixel array ARY has an arrangement in which a video signal DAT from each data signal line SDLi is written into each pixel PIX in synchronism with a scanning signal from each scanning signal line GLj.
The pixel PIX, as shown in FIG. 10, includes a switching element SW, a liquid crystal capacitor CL and an auxiliary capacitor Cs. A pixel capacitor Cp is the sum of the liquid crystal capacitor CL and the auxiliary capacitor Cs.
The data signal line driving circuit SD makes sampling of the video signal DAT inputted by an analog switch, in synchronism with a timing signal such as a clock signal CKS and a data start signal SPS, and writes the received video signal DAT into each data signal line SDLi as required.
The scanning signal line driving circuit GD successively selects the scanning signal line GLj in synchronism with the timing signal such as a clock signal CKG, a scanning start signal SPG and a pulse width control signal PWC, and carries out opening and closing of the switching element SW within the pixel PIX, thereby writing the video signal DAT which was inputted to each data signal line SDLi into each pixel PIX, and holding the video signal DAT which was written into the capacitors within each pixel PIX.
The pre-charging circuit PC makes sampling of a pre-charging voltage PCV which was inputted in synchronism with a timing of a pre-charging control signal PCC, and writes the pre-charging voltage PCV before the video signal DAT is written into each data signal line SDLi. By repeating the foregoing operations, an image can be displayed in the pixel array ARY.
Further, when displaying an image in the wide mode, as shown in FIG. 24, black display is carried out in the upper and lower parts of the 4:3 screen. Here, a signal voltage which is the equivalent of the video signal DAT for the black display is added to the pre-charging voltage PCV within a vertical retrace line period of the video signal DAT, and the voltage is supplied from the pre-charging circuit PC to each data signal line. On the other hand, the clock signal CKG of the scanning signal line driving circuit is driven at a frequency which is four times a frequency of the clock signal CKG in a display area. This, accordingly, causes the pulse width control signal PWC to be also inputted at a frequency which is four times a frequency thereof, thereby driving the scanning signal line. The signal voltage that is the equivalent of the video signal DAT for the black display supplied from the pre-charging circuit PC to each data signal line is written into the pixel, thereby forming a black display area.
FIGS. 22 and 23 show timing charts of the foregoing operations. In FIGS. 22 and 23, the video signal DAT is inputted in synchronism with the clock signal CKS (not shown) and the data start signal SPS in the data signal line driving circuit SD. A driving method of a horizontal line reversal system is adopted in this example, where, in the wide mode, in order to thin out data in an effective pixel area 1H, gate scanning is partially suspended, and the reversal occurs for every line on the screen. A video signal having a positive polarity is written into a line which corresponds to a scanning signal line GL2j-1 (j=15 to (n/2−14), provided n is an even number), while a video signal having a negative polarity is written into a line which corresponds to a scanning signal GL2j. Further, in a horizontal retrace line period, the data signal line SDLi (i=1 to m) is charged to the pre-charging voltage PCV by the pre-charging control signal PCC. Note that, polarities of the pre-charging voltage PCV and the video signal DAT to be written next are the same.
However, in the foregoing image display device, though provision of the current amplifying section Buffer enables stable supply of the pre-charging voltage PCV, yet there arises a problem that the current amplifying section Buffer increases power consumption.